Add a workaround to custom_inclusive_scan_over_group

[antonwolfy]

There is IGC bug identified when using custom_inclusive_scan_over_group inside accumulator SYCL kernels on ARL GPU.
The issue is that IGC incorrectly optimized the code, cause work-item=0 initialized __scan_val with zero instead of identity value.

This PR proposes to implement a workaround which adds SYCL atomic fence. That works since the explicit memory fence prevents reordering/elimination, but leads to slight overhead.

Note, no new test added, since test_tensor_accumulation.py::test_logcumsumexp_basic and test_tensor_accumulation.py::test_cumulative_logsumexp_closed_form[fpdt0] already cover the issue and failed without the w/a in place.

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• Have you tested your changes locally for CPU and GPU devices?
• Have you made sure that new changes do not introduce compiler warnings?
• Have you checked performance impact of proposed changes?
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[github-actions]

Deleted rendered PR docs from intelpython.github.com/dpctl, latest should be updated shortly. 🤞

[coveralls]

coverage: 86.248%. remained the same — add-w/a-to-custom_inclusive_scan_over_group into master

[github-actions]

Array API standard conformance tests for dpctl=0.22.0dev1=py310h93fe807_52 ran successfully.
Passed: 1248
Failed: 43
Skipped: 89

[github-actions]

Array API standard conformance tests for dpctl=0.22.0dev1=py310h93fe807_53 ran successfully.
Passed: 1246
Failed: 45
Skipped: 89

[ndgrigorian]

aside from possibility of changing which memory_order is used this LGTM

[github-actions]

Array API standard conformance tests for dpctl=0.22.0dev1=py310h93fe807_54 ran successfully.
Passed: 1247
Failed: 44
Skipped: 89