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@VLSIDA

VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

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  1. OpenRAM OpenRAM Public

    An open-source static random access memory (SRAM) compiler.

    Python 1k 256

  2. chip-tutorials chip-tutorials Public

    Python 9 5

  3. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

    Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

    OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

    Verilog 1

  4. OpenROAD OpenROAD Public

    Forked from The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow

    Verilog 7

  5. HighTide HighTide Public

    Verilog 8 8

  6. cocotbext-ams cocotbext-ams Public

    An analog simulator bridge for cocotb — open-source mixed-signal co-simulation

    Python 6 1

Repositories

Showing 10 of 40 repositories
  • HighTide Public
    VLSIDA/HighTide’s past year of commit activity
    Verilog 8 8 9 3 Updated Apr 9, 2026
  • OpenRAM Public

    An open-source static random access memory (SRAM) compiler.

    VLSIDA/OpenRAM’s past year of commit activity
    Python 1,035 BSD-3-Clause 256 51 (2 issues need help) 9 Updated Apr 8, 2026
  • skillz Public

    Claude SKILL files for project and research review.

    VLSIDA/skillz’s past year of commit activity
    Makefile 0 BSD-3-Clause 0 0 0 Updated Apr 7, 2026
  • gf180mcu-adpll Public

    All-Digital PLL for GF180MCU using standard cells

    VLSIDA/gf180mcu-adpll’s past year of commit activity
    Python 0 Apache-2.0 0 0 0 Updated Apr 3, 2026
  • OpenROAD Public Forked from The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow

    VLSIDA/OpenROAD’s past year of commit activity
    Verilog 7 BSD-3-Clause 867 0 0 Updated Mar 27, 2026
  • lithosim Public

    This is a very basic lithography simulation and pixel-based OPC tool.

    VLSIDA/lithosim’s past year of commit activity
    Python 47 BSD-3-Clause 9 0 0 Updated Mar 19, 2026
  • cocotbext-ams Public

    An analog simulator bridge for cocotb — open-source mixed-signal co-simulation

    VLSIDA/cocotbext-ams’s past year of commit activity
    Python 6 BSD-3-Clause 1 0 0 Updated Mar 19, 2026
  • bsg_fakeram Public Forked from bespoke-silicon-group/bsg_fakeram

    fakeram generator for use by researchers who do not have access to commercial ram generators

    VLSIDA/bsg_fakeram’s past year of commit activity
    Python 0 BSD-3-Clause 16 0 1 Updated Mar 5, 2026
  • asap7_bb_pdk Public Forked from YZU-EDALAB/asap7_bb_pdk

    Modified ASAP7 PDK with Buried Power Rail (BPR) and Backside Metal (BSM) technologies.

    VLSIDA/asap7_bb_pdk’s past year of commit activity
    HCL 0 1 0 0 Updated Feb 23, 2026
  • VLSIDA/chip-tutorials’s past year of commit activity
    Python 9 Apache-2.0 5 0 1 Updated Jan 29, 2026

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