HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

[TECS'23] A project on the co-design of Accelerators and CNNs.

A high-performance infrastructure framework for distributed systems simulation based on the IEEE-1516 HLA Spec. and NASA DSES.

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

[TCAD'23] TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

The Google Solution Challenge is an annual competition that invites students and developers to solve real-world problems using Google technologies.This repository is your go-to resource for all the information you need to participate in this exciting solution Challenge.

[TMC'23] EdgeTran: Device-Aware Co-Search of Transformers and Mobile Platforms

DUB Sparsity for Crossbars

RTL design of Cellular Automaton for FPGA

FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.

Policy Indexed Contiguous Allocation System (PICAS) is a policy driven and phase aware layered memory allocator with tracing, safety fallbacks, and sanitizer-tested builds.

Educational 6-bit CPU implemented in VHDL with custom ISA and testbench

Resource-efficient image and video processing for embedded and FPGA-based systems. Hardware (VHDL) and software implementations, simulations, and didactic tools (2011–2014). Archived.

Connect6 Game Solver

Hardware–software codesign of a 4×4 matrix operation accelerator on the DE1-SoC FPGA using a custom Avalon-MM peripheral and Nios II processor, with performance comparison against software execution.

HLS based Cordic Accelerator

FPGA-accelerated 2D convolution system using Vitis HLS, Vivado, and PYNQ. Includes a streaming AXI-based accelerator, DMA integration, and end-to-end benchmarking against a software baseline.

HeatSync is an IoT-enabled Raspberry Pi thermostat with a 3.5″ touchscreen interface, real-time DHT22 sensor monitoring, and adaptive heating/cooling control (automatic or manual) with built-in logging.

This repository contains various HW/SW Co-Design projects, where hardware acceleration is combined with software control to optimize performance and flexibility.